MEMS packages and methods of manufacture thereof

ABSTRACT

Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.

BACKGROUND

The term micro electromechanical system (MEMS) or micro mechanicalsystem/structure is often used to refer to small integrated devices orsystems that combine electrical and mechanical components. When focusingon the micro mechanical parts, the term “micro mechanical system” may beused to describe small integrated devices or systems which comprises oneor more micro mechanical elements and possibly, but not necessarily,electrical components and/or electronic components.

Micro mechanical systems may be used as, for example, actuators,transducers or sensors, e.g. pressure sensors. Pressure sensors arenowadays mass products in automobile electronics and consumer goodselectronics. For many of these applications, systems are used in whichthe MEMS sensor is controlled and/or operated with the aid of anapplication-specific integrated circuit (ASIC). In such examples, theMEMS sensor and the ASIC may be included in a MEMS package.

The mechanically active elements of a MEMS package may typically requirerelatively complex structures, such as recesses, beams, cantilevers,undercuts, cavities etc. Possibly, a relatively high number ofmanufacturing steps are required. Furthermore, the process used formanufacturing the MEMS package may need to be compatible with possiblesubsequent manufacturing steps that are used for creating electricaland/or electronic components, for example. Consequently, improvements inmethods of manufacturing a MEMS package may be required.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A and 1B show a single-sided wafer level microelectromechanicalsystems (MEMS) package, in accordance with an embodiment.

FIGS. 2A to 2F show a process flow illustrating a method ofmanufacturing a single-sided wafer level MEMS package, in accordancewith an embodiment.

FIG. 3 shows a double-sided wafer level MEMS package, in accordance withan embodiment.

FIGS. 4A to 4F show a process flow illustrating a method ofmanufacturing a double-sided wafer level MEMS package, in accordancewith an embodiment.

FIG. 5 shows a single-sided chip-on-wafer MEMS package, in accordancewith an embodiment.

FIGS. 6A to 6E show a process flow illustrating a method ofmanufacturing a single-sided chip-on-wafer MEMS package, in accordancewith an embodiment.

FIG. 7 shows a double-sided chip-on-wafer MEMS package, in accordancewith an embodiment.

FIGS. 8A to 8E show a process flow illustrating a method ofmanufacturing a double-sided chip-on-wafer MEMS package, in accordancewith an embodiment.

FIG. 9 shows a single-sided chip-on-wafer MEMS package having one ormore through-vias in a MEMS cap, in accordance with an embodiment.

FIG. 10 shows a single-sided chip-on-wafer MEMS package having an analogchip, in accordance with an embodiment.

FIGS. 11A to 11F show a process flow illustrating a method ofmanufacturing a single-sided chip-on-wafer MEMS package having one ormore third through-vias, in accordance with an embodiment.

FIG. 12 shows a double-sided chip-on-wafer MEMS package having one ormore through-vias in a MEMS cap, in accordance with an embodiment.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and stacks are described belowto simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1A shows a wafer level microelectromechanical systems (MEMS)package 100, in accordance with one or more embodiments. The wafer levelMEMS package 100 may comprise a MEMS wafer 102 disposed between acapping wafer 104 and a device wafer 106. In the example shown in FIG.1A, the MEMS wafer 102 and the device wafer 106 may have substantiallyequal widths W1, W2. In some embodiments, a width of the MEMS wafer 102and a width of the device wafer are in a range from about 8 inches toabout 18 inches. In some embodiments, a width of the MEMS wafer is in arange from about 6 inches to about 12 inches, and a width of the devicewafer is in a range from about 8 inches to about 18 inches.

The MEMS wafer 102 may comprise a plurality of MEMS devices 102-1,102-2, which may be arranged laterally adjacent to each other. In theexample shown in FIG. 1A, the plurality of MEMS devices 102-1, 102-2includes a first MEMS device 102-1 and a second MEMS device 102-2.However, in other embodiments, the number of MEMS devices formed in theMEMS wafer 102 may be more than two (e.g. three, four, five, tens of,etc.). In some embodiments, the plurality of MEMS devices 102-1, 102-2of the MEMS wafer 102 may be arranged as a matrix in the MEMS wafer 102.The first MEMS device 102-1 and the second MEMS device 102-2 may, as anexample, be a first MEMS chip and a second MEMS chip, respectively.Consequently, the MEMS wafer 102 may be a wafer including a plurality ofMEMS chips that have not been singulated or separated from each other.

The MEMS wafer 102 may comprise a semiconductor material, a polymer, ametal, a ceramic, combinations thereof, or the like. In an embodimentwhere the MEMS wafer 102 comprises semiconductor material, thesemiconductor material may include an elementary semiconductor (e.g.including silicon and/or germanium in crystal), a compound semiconductor(e.g. including at least one of oxide, silicon nitride, silicon carbide,gallium arsenic, gallium phosphide, indium phosphide, indium arsenide,or indium antimonide), an alloy semiconductor (e.g. including at leastone of Cu, Al, AlCu, W, Ti, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP,or GaInAsP), or combinations thereof. In an embodiment where the MEMSwafer 102 comprises a polymer, the polymer may include an epoxy, apolyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), combinationsthereof, or the like. In an embodiment where the MEMS wafer 102comprises a ceramic, the ceramic may comprise nitrides of silicon,aluminum and/or titanium, silicon carbide, combinations thereof, or thelike.

The MEMS wafer 102 may include one or more movable elements 108 formedtherein. In the example shown in FIG. 1A, only two movable elements 108are shown; however, in other embodiments, the number of movable elements108 may be less than two (e.g. one) or may be more than two (e.g. three,four, five, six, or more). In some embodiments, the each of theplurality of MEMS devices 102-1, 102-2 of the MEMS wafer 102 maycomprise at least one movable element 108. For example, in theillustration of FIG. 1A, the first MEMS device 102-1 and the second MEMSdevice 102-2 each comprise a movable element 108. The movable element108 may, as an example, be a flexible membrane (e.g. in a deformablemirror device formed in the MEMS wafer 102), a cantilevered beam (e.g.in a motion sensor formed in the MEMS wafer 102), a series of fingers ina comb structure (e.g. in an accelerometer formed in the MEMS wafer102), or the like.

The movable element 108 may be formed by patterning portions of the MEMSwafer 102 (e.g. using lithographic and/or etching processes). In orderto allow for free movement of the movable element 108 in a threedimensional space, the MEMS wafer 102 may include standoff regions 110(e.g. pillars) that create a first gap G1 (e.g. a first air gap) betweenthe movable element 108 and the device wafer 106 (e.g. a surface of thedevice wafer 106 closest in proximity to the movable element 108).Alternatively or additionally, the capping wafer 104 may have a cavity112 formed therein in order to allow for free movement of the movableelement 108. The cavity 112 of the capping wafer 104 may be aligned withthe movable element 108 of the MEMS wafer 102, as shown in FIG. 1A.

Referring now to the device wafer 106 of the wafer level MEMS package100, the device wafer 106 may have one or more first devices 114 formedtherein. In an embodiment, the device wafer 106 may be anapplication-specific integrated circuit (ASIC) wafer, and the one ormore first devices 114 may be one or more ASIC devices. In anembodiment, the one or more ASIC devices may be configured to perform asingle function. In another embodiment, the one or more ASIC devices maybe configured to perform a combination of functions. In such anembodiment, the device wafer 106 may be a combo ASIC device wafer.

The device wafer 106 may comprise a substrate 116 having the one or morefirst devices 114 formed therein (e.g. as shown in the example of FIG.1A) or thereon. The substrate 116 may comprise a semiconductor material,which may comprise one or more of the semiconductor materials describedabove in respect of the MEMS wafer 102. The device wafer 106 maycomprise a plurality of dielectric layers 118 (e.g. stacked dielectriclayers) disposed at a first major surface 116 a of the substrate 116. Asan example, the dielectric layer 118 in closest proximity to thesubstrate 116 may be an inter-layer dielectric (ILD) layer of the devicewafer 106. The plurality of dielectric layers 118 may have a pluralityof interconnect structures 120 formed therein. The plurality ofinterconnect structures 120 may comprise a plurality of metal layers andone or more vias interconnecting the plurality of metal layers. As anexample, the metal layer farthest in distance from the substrate 116 maybe a topmost metal layer of the device wafer 106, while the metal layerclosest in distance to the substrate 116 may be a bottommost metal layerof the device wafer 106. The plurality of interconnect structures 120may comprise a conductive material such as a metal or a metal alloy. Asan example, the plurality of interconnect structures 120 may comprisecopper, gold, aluminum, an alloy thereof, or the like.

The device wafer 106 may further include one or more device plugs 121disposed in a layer of the plurality of dielectric layers 118. As anexample, the one or more device plugs 121 may be disposed in the ILDlayer of the device wafer 106 (e.g. the dielectric layer in closestproximity to the substrate 116). The one or more device plugs 121 mayserve to electrically connect the one or more first devices 114 to theplurality of interconnect structures 120 disposed in the plurality ofdielectric layers 118. The one or more device plugs 121 may comprisesimilar materials as the plurality of interconnect structures 120.

The MEMS wafer 102 may be bonded to the device wafer 106 by a pluralityof inter-wafer connectors 122 disposed between the MEMS wafer 102 andthe device wafer 106. As an example, the plurality of inter-waferconnectors 122 may be bonded to the standoff regions 110 of the MEMSwafer 102 and also to the topmost metal layer of the device wafer 106,thereby attaching the MEMS wafer 102 and the device wafer 106 to eachother, as shown in FIG. 1A. The plurality of inter-wafer connectors 122may comprise a eutectic material. For example, the plurality ofinter-wafer connectors 122 may comprise a lead-based solder material(e.g. Pb—Sn compositions); a lead-free solder material (e.g. includingInSb); a tin, silver, and copper (SAC) composition; a titanium, tin, andcopper composition; copper, nickel and tin compositions; combinationsthereof; or the like. In some embodiments, the plurality of inter-waferconnectors 122 may comprise a plurality of layers by process of electrochemical plating (ECP); metal deposition; combinations thereof. As anexample, in an embodiment where the plurality of inter-wafer connectors122 comprises a titanium, tin, and copper composition, a respectiveinter-wafer connector 122 may comprise as a first layer comprisingtitanium, a second layer comprising tin, and a third layer comprisingcopper (e.g. as shown in the example of FIG. 2A).

Referring now to the capping wafer 104 of the wafer level MEMS package100, the capping wafer 104 may include a semiconductor substrate 124 andan oxide layer 126 disposed on a major surface 124 a of thesemiconductor substrate 124 that faces the MEMS wafer 102. The oxidelayer 126 may be formed conformally over the major surface 124 a, andthus, may line the cavity 112 formed in the capping wafer 104. Thesemiconductor substrate 124 may comprise one or more of thesemiconductor materials described above in respect of the MEMS wafer102. The oxide layer 126 may comprise an oxide of a semiconductormaterial (e.g. silicon oxide). The capping wafer 104 may be bonded tothe MEMS wafer 102 by fusion bonding that may be established between thematerial of the oxide layer 126 on both the capping device 106 and theMEMS chip 102.

The wafer level MEMS package 100 may further include a firstredistribution layer (RDL) 128 disposed at a second major surface 116 bof the substrate 116 opposite the first major surface 116 a. The firstRDL 128 may include conductive structures 128 r (e.g. contact pads,conductive traces, UBMs, or the like) that may be partially or fullydisposed within an insulating layer 128 d (e.g. a dielectric layer). Insome embodiments, the insulating layer 128 d may comprise a plurality ofsub-layers (e.g. a plurality of dielectric sub-layers). The conductivestructures 128 r may comprise similar materials as the plurality ofinterconnect structures 120. In the example of FIG. 1A, the first RDL128 is shown as being a multi-level structure having conductivestructures 128 r formed over a plurality of layers or levels. However,in other embodiments, the first RDL 128 may be a single-level structurehaving a single level conductive structure 128 r (e.g. a conductivetrace, as shown in FIG. 3).

The first RDL 128 may be electrically connected to the plurality ofinterconnect structures 120 by one or more via structures 130, whichextend through the substrate 116 and one or more of the plurality ofdielectric layers 118 (e.g. the ILD layer) of the device wafer 106. Asan example, the one or more via structures 130 may extend between thesecond major surface 116 b and the first major surface 116 a of thesubstrate 116, and may further extend into one or more of the pluralityof dielectric layers 118 from the first major surface 116 b of thesubstrate 116, as shown in the example of FIG. 1A. A first end of theone or more via structures 130 may be electrically and/or physicallycoupled to the plurality of interconnect structures 120 disposed in theplurality of dielectric layers 118 (e.g. the bottom most metal layer),while a second end may be electrically and/or physically coupled to theconductive structures 128 r of the first RDL 128, thereby electricallyconnecting the first RDL 128 and the plurality of interconnectstructures 120 to each other. The one or more via structures 130 maycomprise similar materials as the plurality of interconnect structures120.

The wafer level MEMS package 100 may further include a plurality ofconnectors 132 formed at a surface of the first RDL 128 facing away fromthe device wafer 106. In the example shown in FIG. 1A, the plurality ofconnectors 132 may be a ball-grid array (BGA). In other embodiments, theplurality of connectors 132 may include bumps, pillars, combinationsthereof, or the like. The plurality of connectors 132 may include anelectrically conductive material (e.g. a metal or metal alloy). Forexample, the plurality of connectors 132 may include a solder material.By way of another example, the plurality of connectors 132 may includeat least one of tin, nickel, lead, copper, gold, silver, zinc, bismuth,magnesium, antimony, indium or an alloy thereof. In an embodiment, atleast one connector of the plurality of connectors 132 may beelectrically and/or physically connected to one or more of theconductive structures 128 r of the first RDL 128.

In the embodiment shown in FIG. 1A, the plurality of connectors 132formed at the surface of the first RDL 128 facing away from the devicewafer 106 may be a BGA. However, in another embodiment (e.g. as shown inthe example of FIG. 1B), the plurality of connectors 132 may be replacedwith a plurality of pads 134, which may, as an example, be a land gridarray (LGA). The plurality of pads 134 may comprise similar materials asthe plurality of interconnect structures 120.

FIGS. 2A to 2F show a process flow illustrating a method ofmanufacturing a wafer level MEMS package, in accordance with one or moreembodiments. The process flow shown in FIG. 2A to FIG. 2F may, forexample, be used to manufacture the wafer level MEMS packages 100 shownin FIGS. 1A and 1B. As shown in FIG. 2A, the MEMS wafer 102 comprisingthe plurality of MEMS devices 102-1, 102-2 may be attached or bonded tothe capping wafer 104, e.g. by fusion bonding that may exist betweenmaterial of the oxide layer 126 of the capping wafer 104 and thematerial of the MEMS wafer 102.

The capping wafer 104 may be formed separately from the MEMS wafer 102.For example, the semiconductor substrate 124 of the capping wafer 104may be patterned (e.g. by an etching process) to form the cavities 112.Thereafter, the oxide layer 126 may be formed to line the semiconductorsubstrate 124 and the cavities 112 formed therein. In an embodiment, theoxide layer 126 may be formed by an oxidation process that may beapplied to the semiconductor substrate 124. In another embodiment, theoxide layer 126 may be formed by a deposition process (e.g. conformaldeposition process). The semiconductor substrate 124 of the cappingwafer 104 may have a first thickness T1, which may be a thickness of thesemiconductor substrate 124 in a region of the semiconductor substrate124 outside the cavity 112. The first thickness T1 may be in a rangefrom about 300 micrometers to about 600 micrometers to control thedesired warpage of MEMS wafer 102, although other thicknesses may bepossible as well in other embodiments.

Referring to the MEMS wafer 102 shown in FIG. 2A, in some embodiments,the standoff regions 110 and the movable element 108 may be formed inthe MEMS wafer 102 prior to its attachment or bonding to the cappingwafer 104 thereafter. However, in other embodiments, a substrate (e.g.comprising a semiconductor material, a polymer, a metal, a ceramic,combinations thereof, or the like) may initially be attached or bondedto the capping wafer 104 (e.g. the oxide layer 126 of the capping wafer104). Subsequently, the substrate may be processed (e.g. patternedand/or etched) to form the standoff regions 110 and the movable elements108 of the MEMS wafer 102. In such an embodiment, the capping wafer 104having the cavities 112 formed therein may additionally serve as acarrier to provide mechanical and/or structural support for the MEMSsubstrate during formation of the movable element 108 and the standoffregions 110.

As shown in FIG. 2A, the movable element 108 of the MEMS wafer 102 maybe aligned with the cavity 112 of the capping wafer 104, e.g. in orderto allow for free movement of the movable element 108 during operationof the MEMS wafer 102. Consequently, in the embodiment where thestandoff regions 110 and the movable element 108 are formed in the MEMSwafer 102 prior to attachment or bonding to the capping wafer 104, themovable elements 108 of the MEMS wafer 102 may be aligned with thecavities 112 of the capping wafer 104 prior to and/or while bonding orattaching the capping wafer 104 and the MEMS wafer 102 to each other.However, in the embodiment where the standoff regions 110 and themovable elements 108 are formed after bonding a MEMS substrate to thecapping wafer 104, the movable elements 108 may be formed in regions ofthe substrate that overlie the cavities 112 of the capping wafer 104.The standoff regions 110 of the MEMS wafer 102 may be disposed at amajor surface 200 a of the MEMS wafer 102 facing away from the cappingwafer 104. The standoff regions 110 may extend from the major surface200 a by a first distance D1, which may be in a range from about 1micrometer to about 10 micrometers. In some embodiments, a secondthickness T2 of the MEMS wafer 102 (e.g. in a region of the MEMS wafer102 that is laterally separated from the standoff regions 110) may be ina range from about 10 micrometers to about 50 micrometers, althoughother thicknesses may be possible as well in other embodiments.

As shown in FIG. 2A, the plurality of inter-wafer connectors 122 may beformed over a surface of the standoff regions 110. As an example, theplurality of inter-wafer connectors 122 may be formed on a surface ofthe standoff regions 110 facing away from the capping wafer 104. In theexample of FIG. 2A, the plurality of inter-wafer connectors 122 is shownas comprising a plurality of layers. For example, the plurality ofinter-wafer connectors 122 may comprise a first layer (e.g. bottommostlayer) comprising titanium, a second layer comprising copper, a thirdlayer comprising nickel, and a fourth layer comprising tin. In the otherembodiments, the inter-wafer connectors 122 may comprise a first layer(e.g. bottommost layer) comprising titanium, a second layer comprisingcopper, a third layer comprising tin. The plurality of inter-waferconnectors 122 may be formed on the standoff regions 110 by deposition,evaporation, electroplating, printing, solder transfer, a combinationthereof, or the like. The plurality of inter-wafer connectors 122 mayextend from the standoff regions 110 by a second distance D2, which maybe in a range from about 0.1 micrometer to about 2 micrometers, althoughother distances may be possible as well. In some embodiments, theplurality of inter-wafer connectors 122 may have a width (e.g. measuredin a direction substantially perpendicular to the second distance D2)that may be in a range from about 5 micrometers to about 100micrometers, although other widths may be possible as well.

FIG. 2B shows the device wafer 106, which may be processed separatelyfrom the arrangement shown in FIG. 2A. As shown in FIG. 2B, openings 202may be formed in a dielectric layer of the plurality of dielectriclayers 118 of the device wafer, e.g. by an etching process, althoughother processes for forming the openings 202 may be possible as well.The openings 202 may expose the metal layer farthest in distance fromthe substrate 116 (e.g. the topmost metal layer). Consequently, thedielectric layer in which the openings 202 are formed may be thedielectric layer farthest in distance from the substrate 116 (e.g. thetopmost dielectric layer). In some embodiments, one or more of theopenings 202 may be lined with a conductive liner 204, which may beelectrically connected to the plurality of interconnect structures 120disposed in the plurality of dielectric layers 118 through the metallayer farthest in distance from the substrate 116 (e.g. the topmostmetal layer). The conductive liner 204 may comprise similar materials asthe plurality of interconnect structures 120 and may be formed by adeposition process, a plating process, or the like, although othersuitable process may be possible as well.

As shown in FIG. 2B, at this stage of the process flow, the one or morevia structures 130 may extend partially into the substrate 116, e.g.from the first major surface 116 a of the substrate 116 into an interiorregion of the substrate 116. A third thickness T3 of the device wafer106 may be measured as a distance between the second major surface 116 bof the substrate 116 and the metal layer farthest in distance from thesubstrate 116 (e.g. the topmost metal layer), as shown in FIG. 2B. In anembodiment, the third thickness T3 may be initially about 760micrometers, although other thicknesses may be possible as well in otherembodiments.

Referring to FIG. 2C, the device wafer 106 is attached to the MEMS wafer102 having the capping wafer 104 bonded thereto. In particular, the MEMSwafer 102 may be bonded to the device wafer 106 using the plurality ofinter-wafer connectors 122. In bonding the MEMS wafer 102 and the devicewafer 106 to each other, the plurality of inter-wafer connectors 122 maybe aligned with some of the openings 202 and brought into contact (e.g.physical and/or electrical contact) with the metal layer exposed by theopenings 202. In an embodiment, a thermal compression bonding (TCB)process may also be performed on the plurality of inter-wafer connectors122 to bond the MEMS wafer 102 and the device wafer 106 to each other.The use of the plurality of inter-wafer connectors 122 to bond the MEMSwafer 102 and the device wafer 106 to each other may seal (e.g.hermetically seal) the movable element 108 of the MEMS wafer 102. Asdescribed above in respect of FIG. 1A, the first gap G1 (e.g. a firstair gap) may exist between the movable element 108 and the device wafer106 due to the standoff regions 110. In an embodiment the first gap G1may be in a range from about 1 micrometer to about 10 micrometers. Inlike manner, a second gap G2 (e.g. a second air gap) may exist betweenthe movable element 108 and the oxide layer 126 in the cavity 112 of thecapping wafer 104. In some embodiments, the second gap G2 may besubstantially greater than or equal in dimension to the first gap G1.

Referring to FIG. 2D, the capping wafer 104 may be thinned using a firstthinning process (indicated by arrows 206). In particular, the firstthickness T1 of the semiconductor substrate 124 of the capping wafer 104may be reduced to a thinned first thickness T1′ that may be in a rangefrom about 300 micrometers to about 400 micrometers. The first thinningprocess may be performed using an etching process and/or a planarizationprocess, such as a mechanical grinding process or a chemical mechanicalpolishing (CMP) process.

Referring to FIG. 2E, the device wafer 106 may be thinned using a secondthinning process (indicated by arrows 208), which may be applied to thesecond major surface 116 b of the substrate 116 of the device wafer 106.The second thinning process may expose the one or more via structures130 within the substrate 116. In an embodiment, the third thickness T3of the device wafer 106 may be reduced to a thinned third thickness T3′that may be in a range from about 50 micrometers to about 150micrometers. The second thinning process may be performed using anetching process and/or a planarization process, such as a mechanicalgrinding process or a chemical mechanical polishing (CMP) process.

Referring to FIG. 2F, the first RDL 128 may be formed at the secondmajor surface 116 b of the substrate 116. In some embodiments, the firstRDL 128 may be formed on a carrier and thereafter separated from thecarrier and placed at the second major surface 116 b of the substrate116. This may be followed by a bonding process that bonds the conductivestructures 128 r of the first RDL 128 to the one or more via structures130, and the insulating layer 128 d of the first RDL 128 to thesubstrate 116. In another embodiment, however, the first RDL 128 may beformed by alternately forming insulating material (e.g. dielectricmaterial) of the insulating layer 128 d at the second major surface 116b of the substrate 116 and thereafter forming the conductive structures128 r therein. The insulating material of the insulating layer 128 d maybe formed by spin-on techniques, electro-chemical plating, chemicalvapor deposition (CVD), physical vapor deposition (PVD), atomic layerdeposition (ALD), molecular beam epitaxy CVD, or the like. Theconductive structures 128 r may be formed in the material of theinsulating layer 128 d by a deposition and etching process, a damasceneprocess, a dual damascene process, or the like.

Following the formation of the first RDL 128, the plurality ofconnectors 132 (e.g. shown in FIG. 1A) or the plurality of pads 134(e.g. shown in FIG. 1B) may be formed at a surface of the first RDL 128facing away from the substrate 116. The plurality of connectors 132 maybe formed by exposing (e.g. using an etching process) a plurality ofconductive structures 128 r of the first RDL 128 and forming theplurality of connectors 132 over the exposed plurality of conductivestructures 128 r, e.g. by mounting, printing, ball-drop, or the like.The plurality of pads 134 may be formed by exposing (e.g. using anetching process) a plurality of conductive structures 128 r of the firstRDL 128 and forming the plurality of connectors 132 over the exposedplurality of conductive structures 128 r, e.g. by a deposition and/orplating process. The formation of the plurality of connectors 132 or theplurality of pads 134 may result in the wafer level MEMS package 100shown in FIG. 1A or 1B, respectively. Following this, the wafer levelMEMS package 100 may be diced (e.g. along dicing lines DL, shown in FIG.2F) thereby singulating the device wafer 106, the MEMS wafer 102, andthe capping wafer 104, which may result in a plurality of chip level (orchip scale) MEMS packages 210-1, 210-2. Each of the chip level MEMSpackages 210-1, 210-2 may comprise a MEMS chip (e.g. obtained from thesingulation of the MEMS wafer 102) having a MEMS cap thereon (e.g.obtained from the singulation of the capping wafer 104) and stacked overa device chip (e.g. obtained from the singulation of the device wafer106).

An advantage provided by the wafer level MEMS package 100 shown in FIGS.1A and 1B as well as the process flow illustrated in FIGS. 2A to 2F is awafer-on-wafer level packaging solution for MEMS. Furthermore, theprocess flow illustrated in FIGS. 2A to 2F is a cost effective processthat avoids the cost of using temporary carriers and carrier debonding.The process flow also results in a batch process that achieves highmanufacturing throughput. Furthermore, the integration of a device wafer106 that comprises one or more ASIC devices can achieve small formfactor and higher performance for smart devices, mobile devices,internet-of-things (IoT) and wearable electronics, as examples. As anexample, for respective chip level MEMS package, a single combo ASICdevice can control multiple functions of the respective MEMS devicesincluded in the respective chip level MEMS package. As an example, theMEMS wafer 102 comprises 6 axis motion sensor functions (3 axis inlinear accelerometer, and 3 axis in gyroscope), while device wafer 106comprises two control functions: one for controlling 3 axis linearaccelerometer, the other for controlling 3 axis gyroscope.

In the embodiments shown in FIGS. 1A, 1B, and 2A to 2F, the wafer levelMEMS package 100 may be a single-sided wafer level MEMS package and thechip level MEMS packages obtained therefrom may be single-sided chiplevel MEMS packages. In other words, one side of the device wafer 106(e.g. a top side as shown in the orientation of FIG. 2F) has one or moredevices (e.g. the plurality of MEMS devices 102-1, 102-2) stackedthereon, while another side of the device wafer 106 (e.g. a bottom sideas shown in the orientation of FIG. 2F) is devoid of a stacked device.However, in some embodiments, the wafer level MEMS package may be adouble-sided wafer level MEMS package, where devices are stacked onopposite sides of the device wafer 106. An example of such an embodimentis shown in FIG. 3.

FIG. 3 shows a double-sided wafer level MEMS package 300, in accordancewith one or more embodiments. As shown in FIG. 3, one or more seconddevices 302 may be disposed at the second major surface 116 b of thesubstrate 116 of the device wafer 106 in addition to the MEMS wafer 102that faces the first major surface 116 a of the substrate 116. In anembodiment, the one or more second devices 302 may include a MEMSdevice, an analog device, an energy harvesting device, a sensor device,a logic device, and/or a memory device (e.g. flash device, DRAM, SRAM,SDRAM, or the like), although other devices are possible as well. In theexample of FIG. 3, the first RDL 128 is a single-level structurecomprising a single layer or multiple layers or a single level ormultiple levels conductive structure 128 r. As an example, the singlelevel conductive structure 128 r may be a conductive trace formed at thesecond major surface 116 b of the substrate 116.

As shown in FIG. 3, the one or more second devices 302 may be attachedto the device wafer 106 by an adhesive layer 304 (e.g. an electricallynon-conductive layer). As an example, the adhesive layer 304 may attachthe one or more second devices 302 to the conductive structure 128 r ofthe first RDL 128, thereby attaching the one or more second devices 302to the device wafer 106. The adhesive layer 304 may comprise a glue, apolymer material, a die attach film (DAF), or the like.

The one or more second devices 302 may be encapsulated in a moldingcompound 306. The molding compound 306 may include an insulatingmaterial, which may, for example, include at least one of an epoxymaterial, a polyurethane material or an epoxy blend including two ormore epoxy materials. For example, the molding compound 306 may includeepoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and thelike. The molding compound 306 may be filled with filler particles, suchas silica filler, glass filler or similar fillers.

In the example of FIG. 3, active surfaces 302 a of the one or moresecond devices 302 may face away from the device wafer 106. Metal bumps308 may be formed at the active surfaces 302 a of the one or more seconddevices 302. The metal bumps 308 may comprise similar materials as theplurality of interconnect structures 120. In some embodiments, theactive surfaces 302 a of the one or more second devices 302 may havecontact pads (e.g. I/O pads) formed thereat (not shown in FIG. 3). Insuch embodiments, the metal bumps 308 are disposed over and cover thecontact pads of the one or more second devices 302. Also formed at theactive surface 302 a of a respective second device 302 is a deviceinsulating layer 310 (e.g. comprising a dielectric material) that coversthe active surface 302 a and surrounds the metal bumps 308 of therespective second device 302.

The wafer level MEMS package 300 also comprises a second RDL 312disposed at a surface of the device insulating layer 310 facing awayfrom the one or more second devices 302. The second RDL 312 may includeconductive structures 312 r (e.g. contact pads, vias, conductive traces,UBMs, or the like) that may be partially or fully disposed within aninsulating layer 312 d (e.g. a dielectric layer). The conductivestructures 312 r may comprise similar materials as the plurality ofinterconnect structures 120.

The conductive structures 312 r of the second RDL 312 may beelectrically and/or physically coupled to the metal bumps 308 and mayalso be electrically and/or physically coupled to one or more firstthrough-vias 314 extending through the molding compound 306. The one ormore first through-vias 314 may comprise similar materials as theplurality of interconnect structures 120 and may also be electricallyand/or physically coupled to the first RDL 128. Consequently, the one ormore second devices 302 may be electrically connected to the pluralityof interconnect structures 120 of the device wafer 106 through the metalbumps 308, the second RDL 312, the one or more first through-vias 314,the first RDL 128 and the one or more via structures 130, as shown inFIG. 3. In some embodiments, the plurality of connectors 132 or theplurality of pads 134 may be formed at a surface of the second RDL 312facing away from the one or more second devices 302.

FIGS. 4A to 4F show a process flow illustrating a method ofmanufacturing a double-sided wafer level MEMS package, in accordancewith one or more embodiments. The process flow shown in FIG. 4A to FIG.4F may, for example, be used to manufacture the wafer level MEMS package300 shown in FIG. 3. Referring to FIG. 4A, the structure shown may besimilar to the structure shown in FIG. 2E. For example, the process flowdescribed above in relation to FIGS. 2A to 2E may be performed to arriveat the structure shown in FIG. 4A. As shown in FIG. 4A, the device wafer106 may be thinned using the second thinning process, which may beapplied to the second major surface 116 b of the substrate 116 of thedevice wafer 106. The second thinning process may expose the one or morevia structures 130 within the substrate 116.

Referring to FIG. 4B, the first RDL 128 may be formed at the secondmajor surface 116 b of the substrate 116. As described above in relationto FIG. 3, the first RDL 128 in this example may be a single-levelstructure comprising a single layer or multiple layers or a single levelor multiple levels conductive structure 128 r (e.g. one or moreconductive traces extending along the second major surface 116 b of thesubstrate 116). The first RDL 128 may be formed by a plating process orby a deposition and etching process.

Referring to FIG. 4C, the process flow continues with the formation ofthe one or more first through-vias 314 over the first RDL 128. In someembodiments, the one or more first through-vias 314 may be formeddirectly over the first RDL 128 such that physical contact is madebetween the conductive structure 128 r of the first RDL 128 and the oneor more first through-vias 314. The one or more first through-vias 314may be formed by any suitable techniques such as electroplating. Otherprocesses of formation such as sputtering, evaporation, PECVD and/or thelike may alternatively be used depending upon the desired materials.

Referring to FIG. 4D, the one or more second devices 302 may be placed(e.g. using a pick and place process) over the second major surface 116b of the substrate 116. In particular, the one or more second devices302 may be attached to the second major surface 116 b of the substrate116 by the adhesive layer 304, with the active surface 302 a of the oneor more second devices 302 facing away from the substrate 116. The oneor more second devices 302 may be placed between adjacent via structuresof the one or more first through-vias 314. Accordingly, in someembodiments, at least one via structure 314 may be laterally adjacent toa sidewall of the one or more second devices 302.

Referring to FIG. 4E, the molding compound 306 may be formed toencapsulate the one or more first through-vias 314 and the one or moresecond devices 302. In some embodiments, the molding compound 306 has alateral extent that is substantially equal to a lateral extent of thedevice wafer 106. In some embodiments, the molding compound 306 isshaped or molded using for example, a mold (not shown) which may have aborder or other feature for retaining molding compound 306 when applied.Such a mold may be used to pressure mold the molding compound 306 overthe one or more first through-vias 314 and the one or more seconddevices 302 to force the molding compound 306 into openings, spaced, andrecesses, thereby eliminating air pockets or the like in the moldingcompound 306.

In some embodiments, the molding compound 306 may be formed to cover theone or more first through-vias 314, the device insulating layer 310, andthe metal bumps 308. Accordingly, a thinning process may be performed onthe molding compound 306 to expose the one or more first through-vias314, the device insulating layer 310, and the metal bumps 308. Thethinning process may be performed using an etching process and/or aplanarization process, such as a mechanical grinding process or achemical mechanical polishing (CMP) process. In some embodiments,portions of the one or more first through-vias 314, the deviceinsulating layer 310, and the metal bumps 308 may also be removed by thethinning process. Consequently, surfaces of the one or more firstthrough-vias 314, the device insulating layer 310, and the metal bumps308 may be substantially co-planar with a surface of the moldingcompound 306. Furthermore, as a result of the thinning process, the oneor more first through-vias 314 may extend from the second major surface116 b of the substrate 116 by a third distance D3, which may be in arange from about 5 micrometers to about 10 micrometers.

Referring to FIG. 4F, the process flow continues with the formation ofthe second RDL 312 at a surface of the molding compound 306 facing awayfrom the device wafer 106. In some embodiments, the second RDL 312 maybe formed on a carrier and thereafter separated from the carrier andplaced at the surface of the molding compound 306 facing away from thedevice wafer 106. This may be followed by a bonding process that bondsthe conductive structures 312 r of the second RDL 312 to the one or morefirst through-vias 314 and the metal bumps 308, and the insulating layer312 d of the second RDL 312 to the material of the molding compound 306.In another embodiment, however, the second RDL 312 may be formed byalternately forming insulating material (e.g. dielectric material) ofthe insulating layer 312 d at the surface of the molding compound 306facing away from the device wafer 106 and thereafter forming theconductive structures 312 r therein. The insulating material of theinsulating layer 312 d may be formed by spin-on techniques,electro-chemical plating, chemical vapor deposition (CVD), physicalvapor deposition (PVD), atomic layer deposition (ALD), molecular beamepitaxy CVD, or the like. The conductive structures 312 r may be formedin the material of the insulating layer 312 d by a deposition andetching process, a damascene process, a dual damascene process, or thelike.

Following the formation of the second RDL 312, the plurality ofconnectors 132 (e.g. shown in FIG. 1A) or the plurality of pads 134(e.g. shown in FIG. 1B) may be formed at a surface of the second RDL 312facing away from the substrate 116, e.g. using similar processesdescribed above in respect of FIG. 2F. Following this, the double-sidedwafer level MEMS package 300 may be diced (e.g. along dicing lines DL,shown in FIG. 4F) thereby singulating the device wafer 106, the MEMSwafer 102, the capping wafer 104, and the molding compound 306 havingthe one or more second devices 302 therein. This may result in aplurality of double-sided chip level MEMS packages 410-1, 410-2. Each ofthe double-sided chip level MEMS packages 410-1, 410-2 may comprise aMEMS chip (e.g. e.g. obtained from the singulation of the MEMS wafer102) having a MEMS cap thereon (e.g. obtained from the singulation ofthe capping wafer 104) and stacked over a first surface of a firstdevice chip (e.g. obtained from the singulation of the device wafer106). In addition, a second surface of the device chip may have a seconddevice chip thereat (e.g. the second device 302).

An advantage provided by the wafer level MEMS package 300 shown in FIG.3 as well as the process flow illustrated in FIGS. 4A to 4F is awafer-on-wafer level packaging solution for MEMS. Furthermore, theprocess flow illustrated in FIGS. 4A to 4F is a cost effective processthat avoids the cost of using temporary carriers and carrier debonding.The process flow also results in a batch process that achieves highmanufacturing throughput. Furthermore, the integration of a device wafer106 that comprises one or more ASIC devices can achieve small formfactor and higher performance for smart devices, mobile devices,internet-of-things (IoT) and wearable electronics, as examples. As anexample, for respective chip level MEMS package, a single combo ASICdevice can control multiple functions of the respective MEMS deviceincluded in the respective chip level MEMS package.

In the embodiments shown in FIGS. 1A, 1B, 2A to 2F, 3, and 4A to 4F, awafer level MEMS structure (e.g. MEMS wafer 102) is bonded or attachedto a wafer level device structure (e.g. device wafer 106), e.g. usingthe plurality of inter-wafer connectors 122. In these embodiments, theMEMS wafer 102, the device wafer 106, and the capping wafer 104 aresingulated to form a plurality of chip level MEMS packages. However,there may be other embodiments where a chip level MEMS structure havinga chip level capping structure is bonded or attached to a wafer leveldevice structure (e.g. the device wafer 106). Consequently, in formingthe plurality of chip level MEMS packages, only the wafer level devicestructure (e.g. device wafer 106) may need to be singulated. An exampleof such an embodiment is shown in FIG. 5.

FIG. 5 shows a chip-on-wafer MEMS package 500 comprising MEMS chips 502stacked over a device wafer 506, in accordance with one or moreembodiments. Only two MEMS chips 502 are shown as an example; however,the number of MEMS chips 502 may be more than two (e.g. three, four,five, etc.) in other embodiments. Each of the MEMS chips 502 may, as anexample, be identified with the one of the plurality of MEMS devices102-1, 102-2 of the MEMS wafer 102 described above in respect of FIGS.1A, 1B, 2A to 2F, 3, and 4A to 4F. Furthermore, the device wafer 506may, as an example, be identified with the device wafer 106 describedabove in respect of FIGS. 1A, 1B, 2A to 2F, 3, and 4A to 4F.Consequently, the MEMS chips 502 and the device wafer 506 in FIG. 5 aresimplified illustrations of the MEMS device 102-1 or 102-2 and thedevice 106, respectively. This has been done for the sake of simplicityand to aid in highlighting pertinent features of the embodiment shown inFIG. 5.

As shown in FIG. 5, each of the MEMS chips 502 may be capped by a MEMScap 504, which may be disposed over one or more movable elements 108that may be formed in the MEMS chip 502. The MEMS cap 504 may be a chiplevel structure that may serve to seal (e.g. hermetically seal) the oneor more movable elements 108 of the MEMS chip 502, while providing thesecond gap G2 between a surface of the MEMS cap 504 and a surface of theMEMS chip 502 facing the MEMS cap 504. The MEMS cap 504 differs from thecapping wafer 104 in that the MEMS cap 504 may be a chip level cappingstructure while the capping wafer 104 may be a wafer level cappingstructure. The MEMS cap 504 may comprise similar materials as thecapping wafer 104.

Illustratively, each of the MEMS chips 502 may be obtained bysingulating the MEMS wafer 102 and attaching each of the singulated MEMSdevices to the device wafer 506 such that the singulated MEMS devicesare laterally separated from each other. Also, the MEMS cap 504 may beformed over a respective singulated MEMS device by singulating thecapping wafer 104 covering the singulated MEMS device with thesingulated MEMS cap. The MEMS cap 504 may be bonded or attached to theMEMS chip 502 by a plurality of inter-chip connectors 508 disposedbetween the MEMS cap 504 and the MEMS chip 502. The plurality ofinter-chip connectors 508 may comprise similar materials as theplurality of inter-wafer connectors 122. The MEMS chip 502 may beattached to the device wafer 506 by an adhesive layer 510, which may besimilar in composition to the adhesive layer 304 described above inrespect of FIGS. 1A, 1B, 2A to 2F, 3, and 4A to 4F.

As shown in FIG. 5, the MEMS chip 502 and the MEMS cap 504 may beelectrically connected to each other and to the device wafer 506 by aplurality of wire bonds 512, which may comprise copper, gold, aluminum,an alloy thereof, or the like. The MEMS chip 502, the MEMS cap 504, theadhesive layer 510 and the plurality of wire bonds 512 may beencapsulated in a molding compound 514, which may be similar incomposition to the molding compound 306 described above in relation toFIG. 3.

The plurality of wire bonds 512 may be electrically and/or physicallyconnected to first pads 516 of the device wafer 506, which may bedisposed at a surface of the device wafer 506 facing the MEMS chip 502.The first pads 516 may be electrically connected to second pads 518disposed at a surface of the device wafer 506 facing away from the MEMSchip 502 by one or more second through-wafer vias 520 extending throughthe device wafer 506 and between the first pads 516 and the second pads518. The one or more second through-wafer vias 520, the first pads 516,and the second pads 518 may comprise similar materials as the pluralityof wire bond 512.

As described above, the device wafer 506 may, as an example, beidentified as a simplified illustration of the device wafer 106described above in respect of FIGS. 1A, 1B, 2A to 2F, 3, and 4A to 4F.Accordingly, the one or more second through-wafer vias 520 may, as anexample, extend through the substrate 116 and the plurality ofdielectric layers 118 of the device wafer 106 shown in FIGS. 1A, 1B, 2Ato 2F, 3, and 4A to 4F to electrically connect the first pads 516 andthe second pads 518, which may, as an example, be formed at the secondmajor surface 116 b of the substrate 116 and the metal layer farthest indistance from the substrate 116 (e.g. topmost metal layer),respectively.

In some embodiments, the surface of the device wafer 506 facing the MEMSchip 502 may be a front side of the device wafer 506. In such anembodiment, the first pads 516 of the device wafer 506 may be front sidepads of the device wafer 506. In another embodiment, the surface of thedevice wafer 506 facing away from the MEMS chip 502 may be the frontside of the device wafer 506. In this embodiment, the second pads 518 ofthe device wafer 506 may be the front side pads of the device wafer 506.The chip-on-wafer MEMS package 500 shown in FIG. 5 also includes thefirst RDL 128 comprising the conductive structures 128 r and theinsulating layer 128 d. The first RDL 128 may be formed at the surfaceof the device wafer 506 facing away from the MEMS chip 502. In someembodiments, the plurality of connectors 132 (e.g. BGA) or the pluralityof pads 134 (e.g. LGA) may be formed at the surface of the first RDL 128facing away from the device wafer 106. These structures are not shown inFIG. 5 for the sake of simplicity.

FIGS. 6A to 6E show a process flow illustrating a method ofmanufacturing a chip-on-wafer MEMS, in accordance with one or moreembodiments. The process flow shown in FIG. 6A to FIG. 6E may, forexample, be used to manufacture the chip-on-wafer MEMS package 500 shownin FIG. 5. Furthermore, for the sake of simplicity, the process flowillustrated in FIGS. 6A to 6E show one side (e.g. a left side 500L) ofthe arrangement shown in FIG. 5. However, it should be understood thatthe processes described may be simultaneously applied to both sides 500Land 500R of the structure shown in FIG. 5.

Referring to FIG. 6A, the MEMS chip 502 having the MEMS cap 504 thereonmay be attached or bonded (e.g. using a pick and place process) to thedevice wafer 506 using the adhesive layer 510. As an example, the MEMSchip 502 may be bonded to the surface of the device wafer 506 having thefirst pads 516 formed thereat. As shown in FIG. 6A, at this stage of theprocess flow, the one or more second through-wafer vias 520 extendpartially into the device wafer 506 (e.g. into an interior region of thedevice wafer 506) from the surface of the device wafer 506 having thefirst pads 516.

Referring to FIG. 6B, the plurality of wire bonds 512 may be formed tointerconnect the MEMS cap 504 and the MEMS chip 502 to each other and tothe device wafer 506. Referring to FIG. 6C, the molding compound 514 maybe formed over the device wafer 506 to encapsulate the plurality of wirebonds 512, the MEMS cap 504, the MEMS device 502, and the adhesive layer510. The process used may be similar to that described above in FIG. 4Ein relation to the formation of molding compound 306.

Following this, as shown in FIG. 6D, the device wafer 506 may be thinnedusing a third thinning process (indicated by arrows 602), which may beapplied to the surface of the device wafer 506 facing away from the MEMSchip 502. The third thinning process 602 may expose the one or moresecond through-wafer vias 520. Furthermore, the second pads 518 may beformed over exposed portions of the one or more second through-wafervias 520 (e.g. by a plating process or by a deposition and etchingprocess). The third thinning process 602 may be performed using anetching process and/or a planarization process, such as a mechanicalgrinding process or a chemical mechanical polishing (CMP) process.

Referring to FIG. 6E, the first RDL 128 may be formed at the surface ofthe device wafer 506 having the second pads 518 formed thereat. In someembodiments, the first RDL 128 may be formed on a carrier and thereafterseparated from the carrier and placed at the surface of the device wafer506 having the second pads 518. In another embodiment, however, thefirst RDL 128 may be formed by alternately forming insulating material(e.g. dielectric material) of the insulating layer 128 d at the surfaceof the device wafer 506 having the second pads 518 and thereafterforming the conductive structures 128 r therein. The insulating layer128 d and the conductive structures 128 r of the first RDL 128 may beformed by similar processes described above in respect of FIG. 2F.

Following the formation of the first RDL 128, the plurality ofconnectors 132 (e.g. shown in FIG. 1A) or the plurality of pads 134(e.g. shown in FIG. 1B) may be formed at a surface of the first RDL 128facing away from the device wafer 506, e.g. using the processesdescribed above in respect of FIG. 2F. Following this, the chip-on-waferMEMS package 500 may be diced (e.g. along dicing lines DL, shown in FIG.6E) thereby resulting in a plurality of chip level MEMS packages.

An advantage provided by the wafer level MEMS package 500 shown in FIG.5 as well as the process flow illustrated in FIGS. 6A to 6E is achip-on-wafer level packaging solution for MEMS. Furthermore, theprocess flow illustrated in FIGS. 6A to 6E is a cost effective processthat avoids the cost of using temporary carriers and carrier debonding.The process flow also results in a batch process that achieves highmanufacturing throughput. Furthermore, the integration of a device wafer106 that comprises one or more ASIC devices can achieve small formfactor and higher performance for smart devices, mobile devices,internet-of-things (IoT) and wearable electronics, as examples. As anexample, for respective chip level MEMS package, a single combo ASICdevice can control multiple functions of the respective MEMS deviceincluded in the respective chip level MEMS package.

In the embodiments shown in FIGS. 5 and 6A to 6E, the chip-on-wafer MEMSpackage 500 may be a single-sided chip-on-wafer MEMS package. In otherwords, one side of the device wafer 506 has a chip-level structure (e.g.the MEMS chip 502) stacked thereon, while another side of the devicewafer 506 is devoid of a stacked device. However, in some embodiments,the chip-on-wafer MEMS package may be a double-sided chip-on-wafer MEMSpackage, where chip-level structures are stacked on opposite dies of thedevice wafer 506. An example of such an embodiment is shown in FIG. 7.

FIG. 7 shows a double-sided chip-on-wafer MEMS package 700, inaccordance with one or more embodiments. It is noted that only one side(e.g. a left side) of the double-sided chip-on-wafer MEMS package 700 isshown, and the double-sided chip-on-wafer MEMS package 700 shown in FIG.7 may be replicated to the left or right (e.g. as in FIG. 5). As shownin FIG. 7, the second device 302 may be formed at the surface of thefirst RDL 128 facing away from the MEMS chip 502. Consequently, thedevice wafer 506 may be disposed between the MEMS chip 502 and thesecond device 302. In an embodiment, the second device 302 may include aMEMS device, an energy harvesting device, a sensor device, a logicdevice, an analog device, or a memory device (e.g. flash device, DRAM,SRAM, SDRAM, or the like), although other devices are possible as well.In the example of FIG. 7, the first RDL 128 is a multi-level structurecomprising conductive structures 128 r disposed across a plurality oflayers or levels. However, in some embodiments, the first RDL 128 may bea single level structure comprising a single level conductive structure128 r, which may be a conductive trace.

As shown in FIG. 7, the second device 302 may be attached to the devicewafer 506 by the adhesive layer 304. As an example, the adhesive layer304 may attach the one or more second devices 302 to the insulatinglayer 128 d of the first RDL 128, thereby attaching the second device302 to the device wafer 506.

The second device 302 may be encapsulated in the molding compound 306.In the example of FIG. 7, the active surface 302 a of the second device302 may face away from the device wafer 506. Metal bumps 308 may beformed at the active surface 302 a of the second device 302. In someembodiments, the active surface 302 a of the second device 302 may havecontact pads (e.g. I/O pads) formed thereon (not shown in FIG. 7). Insuch embodiments, the metal bumps 308 are disposed over and cover thecontact pads of the second device 302. Also formed at the active surface302 a is the device insulating layer 310 (e.g. comprising a dielectricmaterial) that covers the active surface 302 a and surrounds the metalbumps 308 of the second device 302.

The double-sided chip-on-wafer MEMS package 700 also comprises thesecond RDL 312 disposed at the surface of the device insulating layer310 facing away from the second device 302. The second RDL 312 mayinclude conductive structures 312 r (e.g. contact pads, vias, conductivetraces, UBMs, or the like) that may be partially or fully disposedwithin the insulating layer 312 d (e.g. a dielectric layer).

The conductive structures 312 r of the second RDL 312 may beelectrically and/or physically coupled to the metal bumps 308 and mayalso be electrically and/or physically coupled to the one or more firstthrough-vias 314 extending through the molding compound 306. The one ormore first through-vias 314 may be electrically and/or physicallycoupled to the first RDL 128. Consequently, the second device 302 may beelectrically connected to the device wafer 506 through the metal bumps308, the second RDL 312, the one or more first through-vias 314, and thefirst RDL 128. Furthermore, the second device 302 may be electricallyconnected to the MEMS chip 502 through the metal bumps 308, the secondRDL 312, the one or more first through-vias 314, the first RDL 128, thesecond pads 518, the one or more second through-wafer vias 520, thefirst pads 516, and the plurality of wire bonds 512. In someembodiments, the plurality of connectors 132 or the plurality of pads134 may also be formed at a surface of the second RDL 312 facing awayfrom the second device 302.

FIGS. 8A to 8E show a process flow illustrating a method ofmanufacturing a double-sided chip-on-wafer MEMS package, in accordancewith one or more embodiments. As an example, the process flow shown inFIGS. 8A to 8E may be used to manufacture the double-sided chip-on-waferMEMS package 700 shown in FIG. 7. Referring to FIG. 8A, the structureshown may be similar to the structure shown in FIG. 6E. For example, theprocess flow described above in relation to FIGS. 6A to 6E may beperformed to arrive at the structure shown in FIG. 8A. As shown in FIG.8A, the first RDL 128 may be formed at the surface of the device wafer506 having the second pads 518 formed thereat.

Referring to FIG. 8B, the process flow continues with the formation ofthe one or more first through-vias 314 over the first RDL 128. Theformation of the one or more first through-vias 314 in FIG. 8B may besimilar to the process described above in relation to FIG. 4C.

Referring to FIG. 8C, the second device 302 may be placed (e.g. using apick and place process) over surface of the first RDL 128 facing awayfrom the device wafer 506. In particular, the second device 302 may beattached to the first RDL 128 by the adhesive layer 304, with the activesurface 302 a of the second device 302 facing away from the device wafer506. The second device 302 may be placed between adjacent via structuresof the one or more first through-vias 314. Accordingly, in someembodiments, at least one via structure 314 may be laterally separatedfrom a sidewall of the second device 302.

Referring to FIG. 8D, the molding compound 306 may be formed toencapsulate the one or more first through-vias 314 and the second device302. In some embodiments, the molding compound 306 has a lateral extentthat is substantially equal to a lateral extent of the device wafer 506.The process used to form the molding compound 306 in FIG. 8D may besimilar to the process described above in relation to FIG. 4E.

Referring to FIG. 8E, the process flow continues with the formation ofthe second RDL 312 at the surface of the molding compound 306 facingaway from the device wafer 506. The process used to form the second RDL312 in FIG. 8E may be similar to the process described above in relationto FIG. 4F. Following the formation of the second RDL 312, the pluralityof connectors 132 (e.g. shown in FIG. 1A) or the plurality of pads 134(e.g. shown in FIG. 1B) may be formed at a surface of the second RDL 312facing away from the device wafer 506. The plurality of connectors 132and the plurality of pads 134 may be formed using similar processesdescribed above in relation to FIG. 4F. Following this, the double-sidedchip-on-wafer MEMS package 700 may be diced (e.g. along dicing line DL,shown in FIG. 8E) thereby singulating the double-sided chip-on-waferMEMS package 700, which may result in a plurality of chip level MEMSpackages.

An advantage provided by the wafer level MEMS package 700 shown in FIG.7 as well as the process flow illustrated in FIGS. 8A to 8E is achip-on-wafer level packaging solution for MEMS. Furthermore, theprocess flow illustrated in FIGS. 8A to 8E is a cost effective processthat avoids the cost of using temporary carriers and carrier debonding.The process flow also results in a batch process that achieves highmanufacturing throughput. Furthermore, the integration of a device wafer106 that comprises one or more ASIC devices can achieve small formfactor and higher performance for smart devices, mobile devices,internet-of-things (IoT) and wearable electronics, as examples. As anexample, for respective chip level MEMS package, a single combo ASICdevice can control multiple functions of the respective MEMS deviceincluded in the respective chip level MEMS package.

The embodiments shown in FIGS. 5, 6A to 6E, 7, 8A to 8E use theplurality of wire bonds 512 to interconnect the MEMS cap 504 and theMEMS chip 502 to each other and to the device wafer 506. However, theinterconnect length among the MEMS cap 504, the MEMS chip 502, and thedevice wafer 506 may be shortened by using an interconnect structureother than the plurality of wire bonds 512. Such an embodiment is shownin FIG. 9.

FIG. 9 shows a single-sided chip-on-wafer MEMS package 900 having one ormore third through-vias 902 in the MEMS cap 504, in accordance with oneor more embodiments. As shown in FIG. 9, the plurality of wire bonds 512is replaced with one or more third through-vias 902 that interconnectthe MEMS cap 504 to the MEMS chip 502 and to the device wafer 506. Inthe example shown in FIG. 9, the MEMS cap 504 is disposed between theMEMS chip 502 and the device wafer 506. The one or more thirdthrough-vias 902 extend from a surface of the MEMS cap 504 proximal theMEMS chip 502 to a surface of the MEMS cap 504 distal the MEMS chip 502.Portions of the one or more third through-vias 902 proximal the MEMSchip 502 may be physically and/or electrically connected to theinter-chip connectors 508, while portions of the one or more thirdthrough-vias 902 distal the MEMS chip 502 may be physically and/orelectrically connected to contact pads 904 disposed at a surface of theMEMS cap 504 facing the device wafer 506. The contact pads 904 maycomprise similar materials as the plurality of interconnect structures120.

As shown in FIG. 9, a third RDL 928 may be disposed between the contactpads 904 and the device wafer 506. In particular, the third RDL 928 maybe disposed at the surface of the device wafer 506 having the first pads516 thereat. In some embodiments, the surface of the device wafer 506having the first pads 516 thereat may be a front side of the devicewafer 506. In such an embodiment, the first pads 516 of the device wafer506 may be front side pads of the device wafer 506. In anotherembodiment, the surface of the device wafer 506 having the second pads518 thereat may be the front side of the device wafer 506. In thisembodiment, the second pads 518 of the device wafer 506 may be the frontside pads of the device wafer 506.

The third RDL 928 may include conductive structures 928 r (e.g. contactpads, conductive traces, UBMs, or the like) that may be partially orfully disposed within an insulating layer 928 d (e.g. a dielectriclayer). In some embodiments, the insulating layer 928 d may comprise aplurality of sub-layers (e.g. a plurality of dielectric sub-layers). Theconductive structures 928 r may comprise similar materials as theplurality of interconnect structures 120. The third RDL 928 may be amulti-level structure having conductive structures 928 r formed over aplurality of layers or levels or the third RDL 928 may be a single-levelstructure having a single level conductive structure 128 r (e.g. aconductive trace). One or more of the conductive structures 928 r of thethird RDL 928 may be physically and/or electrically connected to thefirst pads 516. Furthermore, one or more of the conductive structures928 r of the third RDL 928 may be physically and/or electricallyconnected to conductive elements 906 (e.g. bumps, such as C4 solderbumps or micro-bumps). Conductive elements 906 are disposed between thethird RDL 928 and the MEMS cap 504. The conductive elements 906 maycomprise similar materials as the plurality of connectors 132 and mayfurther be physically and/or electrically connected to the contact pads904.

With the arrangement shown in FIG. 9, the interconnect length among theMEMS cap 504, the MEMS chip 502, and the device wafer 506 may beshortened through the use of the one or more third through-vias 902.This shortening of the interconnect length among the MEMS cap 504, theMEMS chip 502, and the device wafer 506 may allow for low parasitics,high memory bandwidth, and high capacity compared to previousembodiments. This also may result in low power consumption of the MEMSpackage 900 compared to previous embodiments, thus allowing the variousMEMS packages to be used in a variety of applications, such as aninternet-of-things (IoT) and wearable electronics, as examples.

In the embodiment shown in FIG. 9, analog function of the MEMS package900 may be included in the device wafer 506 and/or the MEMS chip 502.However, in another embodiment, the analog function of the MEMS package900 may be partitioned out of the device wafer 506 and/or MEMS chip 502as a separate analog chip. Such an embodiment is shown in FIG. 10.

FIG. 10 shows a single-sided chip-on-wafer MEMS package 1000 having ananalog chip 1002, in accordance with one or more embodiments. As shownin FIG. 10, the analog chip 1002 may be disposed at a surface of theMEMS chip 502 facing away from the MEMS cap 504. The analog chip 1002may be attached to the MEMS chip 502 by an adhesive or through otherchip-to-chip bonding techniques. The one or more third through-vias 902may further extend into the MEMS chip 502 in order to make physicaland/or electrical contact with the analog chip 1002. Consequently, theanalog chip 1002, the MEMS cap 504, and the MEMS chip 502 areelectrically connected to one another and to the device wafer 506.

FIGS. 11A to 11F show a process flow illustrating a method ofmanufacturing a single-sided chip-on-wafer MEMS package having one ormore third through-vias, in accordance with one or more embodiments. Asan example, the process flow shown in FIGS. 11A to 11F may be used tomanufacture the MEMS packages 900 and 1000 shown in FIGS. 9 and 10,respectively. Referring to FIG. 11A, the conductive elements 906 may beformed at the contact pads 904 formed at the surface of the MEMS cap 504facing away from the MEMS chip 502. The conductive elements 906 may beformed at the contact pads 904 by evaporation, electroplating, printing,solder transfer, ball placement, or the like.

Referring to FIG. 11B, the third RDL 928 may be formed at the surface ofthe device wafer 506 having the first pads 516. The third RDL 928 may beformed using similar processes as described above in relation to thefirst RDL 128. As shown in FIG. 11B, at this stage of the process flow,the one or more second through-wafer vias 520 may extend partially intothe device wafer 506, e.g. from the surface of the device wafer 506having the first pads 516 into an interior region of the device wafer506.

Referring to FIG. 11C, the MEMS chip 502 and MEMS cap 504 may be bondedor attached to the third RDL 928 (e.g. using flip-chip bondingtechniques). As described above in relation to FIG. 9, one or more ofthe conductive structures 928 r of the third RDL 928 may be physicallyand/or electrically connected to conductive elements 906. Referring toFIG. 11D, the molding compound 514 may be formed over the third RDL 928to encapsulate the conductive elements 906, the space between the MEMScap 504 and the third RDL 928, the MEMS cap 504, and the MEMS device502. The process used may be similar to that described above in FIG. 4Ein relation to the formation of molding compound 306.

Following this, as shown in FIG. 11E, the device wafer 506 may bethinned using the third thinning process 602, which may be applied tothe surface of the device wafer 506 facing away from the MEMS chip 502.The third thinning process 602 may expose the one or more secondthrough-wafer vias 520. Furthermore, the second pads 518 may be formedover exposed portions of the one or more second through-wafer vias 520(e.g. by a plating process or by a deposition and etching process). Thethird thinning process 602 may be performed using an etching processand/or a planarization process, such as a mechanical grinding process ora chemical mechanical polishing (CMP) process.

Referring to FIG. 11F, the first RDL 128 may be formed at the surface ofthe device wafer 506 having the second pads 518 formed thereat. In someembodiments, the first RDL 128 may be formed on a carrier and thereafterseparated from the carrier and placed at the surface of the device wafer506 having the second pads 518. In another embodiment, however, thefirst RDL 128 may be formed by alternately forming insulating material(e.g. dielectric material) of the insulating layer 128 d at the surfaceof the device wafer 506 having the second pads 518 and thereafterforming the conductive structures 128 r therein. The insulating layer128 d and the conductive structures 128 r of the first RDL 128 may beformed by similar processes described above in respect of FIG. 2F.

Following the formation of the first RDL 128, the plurality ofconnectors 132 (e.g. shown in FIG. 1A) or the plurality of pads 134(e.g. shown in FIG. 1B) may be formed at a surface of the first RDL 128facing away from the device wafer 506, e.g. using the processesdescribed above in respect of FIG. 2F. Following this, the chip-on-waferMEMS package 900 may be diced (e.g. along dicing lines DL, shown in FIG.11F) thereby resulting in a plurality of chip level MEMS packages.

An advantage provided by the wafer level MEMS packages 900 and 1000shown in FIGS. 9 and 10 as well as the process flow illustrated in FIGS.11A to 11F is a chip-on-wafer level packaging solution for MEMS.Furthermore, the process flow illustrated in FIGS. 11A to 11F is a costeffective process that avoids the cost of using temporary carriers andcarrier debonding. The process flow also results in a batch process thatachieves high manufacturing throughput. Furthermore, the integration ofa device wafer 106 that comprises one or more ASIC devices can achievesmall form factor and higher performance for smart devices, mobiledevices, internet-of-things (IoT) and wearable electronics, as examples.As an example, for respective chip level MEMS package, a single comboASIC device can control multiple functions of the respective MEMS deviceincluded in the respective chip level MEMS package.

Furthermore, with the arrangements shown in FIGS. 9 and 10, theinterconnect length among the MEMS cap 504, the MEMS chip 502, and thedevice wafer 506 may be shortened through the use of the one or morethird through-vias 902. This shortening of the interconnect length amongthe MEMS cap 504, the MEMS chip 502, and the device wafer 506 may allowfor low parasitics, high memory bandwidth, and high capacity compared toprevious embodiments. This also may result in low power consumption ofthe MEMS packages 900 and 1000 compared to previous embodiments, thusallowing the various MEMS packages to be used in a variety ofapplications, such as an internet-of-things (IoT) and wearableelectronics, as examples.

In the embodiments shown in FIGS. 9, 10, and 11A to 11F, thechip-on-wafer MEMS packages 900 and 1000 may be a single-sidedchip-on-wafer MEMS package. In other words, one side of the device wafer506 has a chip-level structure (e.g. the MEMS chip 502) stacked thereon,while another side of the device wafer 506 is devoid of a stackeddevice. However, in some embodiments, the chip-on-wafer MEMS package maybe a double-sided chip-on-wafer MEMS package, where chip-levelstructures are stacked on opposite dies of the device wafer 506. Anexample of such an embodiment is shown in FIG. 12.

FIG. 12 shows a double-sided chip-on-wafer MEMS package 1200 having oneor more third through-vias, in accordance with one or more embodiments.It is noted that only one side (e.g. a left side) of the double-sidedchip-on-wafer MEMS package 1200 is shown, and the double-sidedchip-on-wafer MEMS package 1200 shown in FIG. 12 may be replicated tothe left or right (e.g. as in FIG. 5). As shown in FIG. 12, the seconddevice 302 may be formed at the surface of the first RDL 128 facing awayfrom the MEMS chip 502. Consequently, the device wafer 506 may bedisposed between the MEMS chip 502 and the second device 302. In anembodiment, the second device 302 may include a MEMS device, an analogdevice, an energy harvesting device, a sensor device, a logic device,and/or a memory device (e.g. flash device, DRAM, SRAM, SDRAM), althoughother devices are possible as well. In the example of FIG. 12, the firstRDL 128 is a multi-level structure comprising conductive structures 128r disposed across a plurality of layers or levels. However, in someembodiments, the first RDL 128 may be a single level structurecomprising a single level conductive structure 128 r, which may be aconductive trace.

As shown in FIG. 12, the second device 302 may be attached to the devicewafer 506 by the adhesive layer 304. As an example, the adhesive layer304 may attach the one or more second devices 302 to the insulatinglayer 128 d of the first RDL 128, thereby attaching the second device302 to the device wafer 506.

The second device 302 may be encapsulated in the molding compound 306.In the example of FIG. 12, the active surface 302 a of the second device302 may face away from the device wafer 506. Metal bumps 308 may beformed at the active surface 302 a of the second device 302. In someembodiments, the active surface 302 a of the second device 302 may havecontact pads (e.g. I/O pads) formed thereon (not shown in FIG. 12). Insuch embodiments, the metal bumps 308 are disposed over and cover thecontact pads of the second device 302. Also formed at the active surface302 a is the device insulating layer 310 (e.g. comprising a dielectricmaterial) that covers the active surface 302 a and surrounds the metalbumps 308 of the second device 302.

The double-sided chip-on-wafer MEMS package 1200 also comprises thesecond RDL 312 disposed at the surface of the device insulating layer310 facing away from the second device 302. The second RDL 312 mayinclude conductive structures 312 r (e.g. contact pads, vias, conductivetraces, UBMs, or the like) that may be partially or fully disposedwithin the insulating layer 312 d (e.g. a dielectric layer).

The conductive structures 312 r of the second RDL 312 may beelectrically and/or physically coupled to the metal bumps 308 and mayalso be electrically and/or physically coupled to the one or more firstthrough-vias 314 extending through the molding compound 306. The one ormore first through-vias 314 may be electrically and/or physicallycoupled to the first RDL 128. Consequently, the second device 302 may beelectrically connected to the device wafer 506 through the metal bumps308, the second RDL 312, the one or more first through-vias 314, and thefirst RDL 128. Furthermore, the second device 302 may be electricallyconnected to the MEMS chip 502 through the metal bumps 308, the secondRDL 312, the one or more first through-vias 314, the first RDL 128, thesecond pads 518, the one or more second through-wafer vias 520, thefirst pads 516, the third RDL 928, the conductive elements 906, thecontact pads 904, the one or more third through-vias 902, and theplurality of inter-chip connectors 508. In some embodiments, theplurality of connectors 132 or the plurality of pads 134 may also beformed at a surface of the second RDL 312 facing away from the seconddevice 302. The process flow used to manufacture the double-sidedchip-on-wafer MEMS package 1200 may, as an example, be similar to theprocess flow shown in FIGS. 8A to 8E.

The advantages described above in relation to FIGS. 9 and 10 are alsorealized with the embodiment shown in FIG. 12.

According to various embodiments described herein, a method ofmanufacturing a MEMS package is provided. In an embodiment, the methodcomprises: attaching a MEMS structure having a capping structure thereonto a device wafer comprising a plurality of first devices formed thereinto form a wafer level MEMS package; and singulating the device waferhaving the MEMS structure attached thereto to form a plurality of chipscale MEMS packages.

According to various embodiments described herein, a method ofmanufacturing a MEMS package is provided. In an embodiment, the methodcomprises: coupling a MEMS structure having a capping structure thereonto a device wafer comprising a plurality of first devices to form awafer level MEMS package; after the coupling, thinning the wafer levelMEMS package to expose conductive features in the device wafer; forminga first redistribution layer (RDL) at a surface of the thinned waferlevel MEMS package, the first RDL electrically coupled to the exposedconductive features; and singulating the wafer level MEMS package toform a plurality of chip scale MEMS packages.

According to various embodiments described herein, a method ofmanufacturing a MEMS package is provided. In an embodiment, the methodcomprises: disposing a plurality of MEMS devices over a device wafercomprising a plurality of first devices formed therein, the plurality ofMEMS devices electrically coupled to the plurality of first devices;exposing conductive features in the device wafer using a thinningprocess; forming a first redistribution layer (RDL) over a surface ofthe device wafer exposed to the thinning process, the first RDLelectrically coupled to the conductive features in the device layer; anddicing the device wafer and the first RDL to separate the plurality offirst devices from each other and the plurality of MEMS devices fromeach other.

According to various embodiments described herein, a MEMS package isprovided. In an embodiment, the MEMS package comprises: a first devicesubstrate comprising one or more first devices formed therein; a MEMSstructure having a capping structure thereon disposed at a first majorsurface of the first device substrate; and a second device substratecomprising one or more second devices formed therein, the second devicesubstrate disposed at a second major surface of the first devicesubstrate, the second major surface opposite the first major surface.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of manufacturing a microelectromechanical systems (MEMS) package, the method comprising: bonding a capping structure to a MEMS device to form a MEMS structure, wherein the capping structure comprises a substrate and an oxide layer, the substrate having a cavity disposed in a first surface thereof, wherein the oxide layer lines the cavity, and wherein the oxide layer is interposed between the substrate of the capping structure and the MEMS device; attaching the MEMS structure to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.
 2. The method of claim 1, wherein a first one of the plurality of chip scale MEMS packages comprises a first one of the plurality of first devices, and wherein a second one of the plurality of chip scale MEMS packages comprises a second one of the plurality of first devices.
 3. The method of claim 1, wherein the MEMS structure comprises a MEMS wafer comprising a plurality of MEMS devices, and wherein the capping structure comprises a capping wafer comprising the substrate and the oxide layer, the capping wafer having a plurality of cavities lined by the oxide layer, each of the plurality of cavities disposed over a respective one of the plurality of MEMS devices.
 4. The method of claim 3, wherein the singulating further comprises singulating the MEMS wafer and the capping wafer, wherein a first one of the plurality of chip scale MEMS packages comprises a first one of the plurality of MEMS devices, and wherein a second one of the plurality of chip scale MEMS packages comprises a second one of the plurality of MEMS devices.
 5. The method of claim 1, wherein the attaching the MEMS structure to the device wafer comprises: forming a plurality of inter-wafer connectors at standoff regions of the MEMS structure, the standoff regions extending from a major surface of the MEMS structure away from the capping structure; and bonding the plurality of inter-wafer connectors to a metal feature of the device wafer.
 6. The method of claim 5, wherein the bonding the plurality of inter-wafer connectors comprises a thermal compression bond (TCB) process.
 7. The method of claim 1, wherein the MEMS device comprises a MEMS chip, and wherein the capping structure comprises a MEMS cap disposed on a surface of the MEMS chip.
 8. The method of claim 7, wherein the attaching the MEMS structure to the device wafer comprises attaching the MEMS structure to the device wafer using an adhesive layer disposed between the MEMS structure and the device wafer.
 9. The method of claim 8, wherein the MEMS structure is electrically coupled to the plurality of first devices by a plurality of wirebonds.
 10. The method of claim 7, wherein the attaching the MEMS structure to the device wafer comprises bonding the MEMS cap to the device wafer using a plurality of inter-chip connectors disposed between the MEMS cap and the device wafer.
 11. The method of claim 10, wherein the MEMS structure is electrically coupled to the plurality of first devices by one or more through-vias extending through the MEMS cap.
 12. A method of manufacturing a microelectromechanical systems (MEMS) package, the method comprising: bonding a capping structure to a MEMS device to form a MEMS structure, the capping structure having a cavity disposed therein, the cavity disposed over a sensing feature of the MEMS device; forming standoff structures in the MEMS device of the MEMS structure, the standoff structures disposed at a surface of the MEMS structure opposite the capping structure; forming openings in a device wafer comprising a plurality of first devices, wherein the openings are formed in a dielectric layer of the device wafer, wherein the openings expose a metal layer under the dielectric layer, wherein the device wafer is separate from the MEMS structure; after forming the standoff structures and openings, aligning the standoff structures to the openings in the device wafer; after aligning the standoff structures to the openings, coupling the standoff structures of the MEMS structure to the corresponding metal layer of the openings in the device wafer via corresponding inter-wafer connectors to form a wafer level MEMS package, wherein each of the corresponding inter-wafer connectors extends into a corresponding opening and physically contacts a corresponding standoff structure and a metal layer of the corresponding opening in the device wafer; after the coupling, thinning the wafer level MEMS package to expose conductive features in the device wafer; forming a first redistribution layer (RDL) at a surface of the thinned wafer level MEMS package, the first RDL electrically coupled to the exposed conductive features; and singulating the wafer level MEMS package to form a plurality of chip scale MEMS packages.
 13. The method of claim 12, wherein the MEMS structure and the capping structure comprises a MEMS chip and a MEMS cap disposed over the MEMS chip, respectively, and wherein the method further comprises encapsulating the MEMS chip and the MEMS cap in a first molding compound after the coupling and prior to the thinning.
 14. The method of claim 12, further comprising: prior to the singulating, coupling a plurality of second devices on a surface of the first RDL facing away from the device wafer; and encapsulating the plurality of second devices in a second molding compound.
 15. The method of claim 12, wherein a width of the MEMS structure and a width of the device wafer are in a range from about 8 inches to about 18 inches.
 16. The method of claim 12, wherein a width of the MEMS structure is in a range from about 6 inches to about 12 inches, and wherein a width of the device wafer is in a range from about 8 inches to about 18 inches.
 17. A microelectromechanical systems (MEMS) package, comprising: a first device substrate comprising one or more first devices formed therein; a MEMS structure having a capping structure thereon disposed at a first major surface of the first device substrate; and a second device substrate comprising one or more second devices formed therein, the second device substrate disposed at a second major surface of the first device substrate, the second major surface opposite the first major surface, wherein the second device substrate comprises metal bumps formed at an active surface of the second device substrate, wherein the active surface of the second device faces away from the first device substrate, wherein the second device substrate is laterally encapsulated within a first molding compound wherein the first molding compound has a same lateral extent as the first device substrate, wherein the MEMS structure comprises a plurality of standoff regions at the first major surface of the first device substrate, and wherein a sealing connector couples the standoff regions to the first device substrate and provides a sealed cavity between the MEMS structure and the first device substrate.
 18. The MEMS package of claim 17, wherein the MEMS structure and the capping structure are encapsulated in a second molding compound.
 19. The MEMS package of claim 17, further comprising a first redistribution layer (RDL) disposed between the first device substrate and the second device substrate and a second RDL disposed on the active surface of the second device substrate, wherein the one or more first devices and the one or more second devices are electrically coupled by the first RDL and the second RDL.
 20. The MEMS package of claim 17, further comprising an adhesive layer coupling the first device substrate and the second device substrate to each other. 